Multi-value read-only memory cell having an improved signal-to-noise ratio

ABSTRACT

The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M&#34;&#39;) and asymmetrically for storing at least a third state (M&#39;, M&#34;). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.

BACKGROUND OF THE INVENTION

Conventional memory cells can each store 1 bit of information. The twostates of the cell may be, for example, a high or low threshold voltageof the transistor in a 1-transistor memory cell. During the read-outoperation, the bit lines in many known arrangements are initiallyprecharged to a defined voltage. When the cell is driven via the wordline, the charge of the bit line connected to the cell is changed to agreater or lesser extent depending on the state of the cell. In thisway, the information of the cell can be read out via a high or low levelof the bit line. In order to achieve high interference immunity, the twolevels must have the maximum possible voltage difference, for examplepositive supply voltage and 0 volts.

In order to increase the information density, multi-value memory cellshave also occasionally been used, in particular in read-only memories.Multi-value memory cells are memory cells which each have a storagecapacity of more than 1 bit.

The international patent application with the publication number WO82/02977 has disclosed a mask-programmable read-only memory (ROM) inwhose memory cells it is possible to store more than only two logicstates. In order to obtain cells each having the same, minimum size, thelogic states are in this case programmed into the cells by setting thethreshold voltage of the transistor situated in the respective cellseparately in each case.

This necessitates the reliable differentiation between a plurality, forexample four, of different voltage or current values. This means ahigher outlay on circuitry, for example for stabilized referencevoltages, and, above all, a reduced interference immunity. This can alsolead to reduced efficiency. This, presumably, is why multi-value memorycells have not attained any practical significance to date. In modernmemories with a reduced supply voltage, for example with 3.3 V, thedisadvantages cited are even less acceptable.

The document GB-A-2 157 489 discloses a multi-value read-only memorycell which is of symmetrical construction for storing a first or secondstate and of asymmetrical construction for storing a third or fourthstate.

SUMMARY OF THE INVENTION

The invention is based on the object, then, of specifying a multi-valuememory cell in which the minimum possible outlay on circuitry isrequired and in which the signal-to-noise ratio is significantlyimproved in comparison with known multi-value memory cells.

In general terms the present invention is a multi-value read-only memorycell has symmetrical construction for storing one of a first state and asecond state and having asymmetrical construction for storing at least athird state. A MOS field-effect transistor has a source/drain regionsituated in a semiconductor body and has a drain/source region situatedin the semiconductor body. In order to store the first state, a firstcell connection is connected directly to the source/drain region of theMOS field-effect transistor and a second cell connection is connecteddirectly to the drain/source region of the MOS field-effect transistor.In order to store the second state, the first cell connection isconnected via a first component to the source/drain region of the MOSfield-effect transistor, and the second cell connection is connected viaa second component to the drain/source region of the MOS field-effecttransistor. In order to store the third state, the first cell connectionis connected via the first component to the source/drain region of theMOS field-effect transistor, and the second cell connection is connecteddirectly to the drain/source region of the MOS field-effect transistor.In order to store a fourth state, the first cell connection is connecteddirectly to the source/drain region of the MOS field-effect transistorand the second cell connection is connected via the second component tothe drain/source region of the MOS field-effect transistor. A third cellconnection is connected to a gate electrode of the MOS field-effecttransistor, drain/source region, the same doping in order to store thegate electrode being electrically insulated from the semiconductor bodyby an insulation layer. The first component is a first diode and thesecond component is a second diode.

Advantageous developments of the present invention are as follows.

In order to form the first diode, the first cell connection is connectedvia a first supplementary region to the source/drain region of the MOSfield-effect transistor. In order to form the second diode, the secondcell connection is connected via a second supplementary region to thedrain/source region of the MOS field-effect transistor. In order tostore the first state, first and second supplementary regions arebridged by metallic contact links of the first and second connections,which contact links have a deep structure and extend at least as far asthe source/drain region and drain/source region. In order to store thesecond state, both the first and second supplementary regions arecontacted only by metallic contact links of the first and secondconnections, which contact links are planar and extend only at least asfar as the first and second supplementary regions. In order to store thethird state, only the first supplementary region is bridged by ametallic contact link of the first connection, which contact link has adeep structure and extends at least as far as the source/drain region.In order to store the fourth state, only the second supplementary regionis bridged by a metallic contact link of the first connection, whichcontact link has a deep structure and extends at least as far as thedrain/source region.

In another embodiment the memory cell has symmetrical construction forstoring a first state and a second state and asymmetrical constructionfor storing at least a third state. A MOS field effect transistor has asource/drain region situated in a semiconductor body and a drain/sourceregion situated in the semiconductor body. In order to store the firststate a first cell connection is connected directly to the source/drainregion of the MOS field-effect transistor, and a second cell connectionis connected directly to the drain/source region of the MOS field-effecttransistor. In order to store the second state, the first cellconnection connected via a first component to the source/drain region ofthe MOS field-effect transistor and the second cell connection connectedvia a second component to the drain/source region of the MOSfield-effect transistor. In order to store the third state, the firstcell connection is connected via the first component to the source/drainregion of the MOS field-effect transistor, and the second cellconnection is connected directly to the drain/source region of the MOSfield-effect transistor. In order to store a fourth state, the firstcell connection is connected directly to the source/drain region of theMOS field-effect transistor, and the second cell connection is connectedvia the second component to the drain/source region of the MOSfield-effect transistor. In order to store the third state, the firstcell connection is connected via the first component to the source/drainregion of the MOS field-effect transistor, and the second cellconnection is connected directly to the drain/source region of the MOSfield-effect transistor. In order to store a fourth state, the firstcell connection is connected directly to the source/drain region of theMOS field-effect transistor, and the second cell connection is connectedvia the second component to the drain/source region of the MOSfield-effect transistor. A third cell connection connected to a gateelectrode of the MOS field-effect transistor, the gate electrode beingelectrically insulated from the semiconductor body by an insulationlayer. The first component is a first resistor and the second componentis a second resistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures of which like referencenumerals identify like elements, and in which:

FIG. 1 shows illustrations of a memory cell in the four possible states,

FIGS. 2A to 2D show different designs of MOS transistors of a memorycell, for realizing four different memory states,

FIG. 3 shows a different embodiment variant of FIG. 2D,

FIG. 4 shows a circuit diagram of a first further memory cell accordingto the invention,

FIG. 5 shows a sectional representation to explain the production of thememory cell of FIG. 4, and

FIG. 6 shows a circuit diagram of a second further memory cell accordingto the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates memory cells according to the invention with theirrespective cell connections 1, 2 and 3, which memory cells areprogrammed in four different states M, M', M", M"'. In this case, thememory cell with the state M has no marking, the memory cell with thestate M' has a marking in the form of a spot at the cell connection 1,the memory cell with the state M" has a marking in the form of a spot atthe cell connection 2 and the memory cell with the state M"' has amarking in the form of a spot both at the cell connection 1 and the cellconnection 2. The memory cells with the stored states M and M"' aretherefore symmetrical with respect to the cell connections 1 and 2, andthe memory cells with the stored states M' and M" are thereforeasymmetrical with respect to the cell connections 1 and 2.

FIGS. 2A to 2D show by way of example the storage of 4 states in ann-channel transistor, which is situated, for example, in a one-timeprogrammable memory cell (OTP memory cell).

In this case, FIG. 2A shows the unprogrammed symmetrical MOS transistor.In the MOS transistor of FIG. 2B, negative charges have been introducedwithin a region in the gate oxide near to the cell connection 1. Thismeans that a higher gate voltage VG is necessary to produce an inversionchannel underneath this region than under the gate oxide near to thecell connection 2. In simple terms, this means that the thresholdvoltage VT near to the cell connection 1 is locally increased. Duringoperation of an MOS transistor in the saturation region (drain-sourcevoltage VDS>VG-VT), the onset of conductivity is determinedapproximately only by the threshold voltage near to the sourceconnection. By definition, the source connection is that cell connection1 or 2 which has the lower voltage. In the event of driving cellconnection 1 as the source, a high threshold voltage is thus produced,and in the event of driving cell connection 2 as the source, a lowthreshold voltage is consequently produced. In FIG. 2C, the cellconnections 1 and 2 are virtually just changed over from the arrangementof 2B and the relationships are correspondingly reversed. On the otherhand, FIG. 2D shows the case where the threshold voltage is increased onboth sides.

FIG. 3 shows the case where the threshold voltage is increased in theentire channel. The transistors of FIG. 2D and FIG. 3 are equivalent asregards the electrical characteristics, but different programmingmethods can be used, which is, however, explained in more detail below.

The following table indicates, in order for the transistors shown inFIGS. 2A to 2D and FIG. 3, the threshold voltage VT as a function of thepolarity of the voltage VDS at the cell connections 1 and 2, and alsothe associated cell information as a 2-bit number. It is noteworthy herethat the signal to be read out has the same high signal-to-noise ratioas a conventional 1-bit memory cell.

    ______________________________________                                        VT where       VT where      Cell                                             VDS = V21 > 0  VDS = V12 > 0 information                                      ______________________________________                                        low            low           0 0 M                                            low            increased     0 1 M'                                           increased      low           1 0 M"                                           increased      increased     1 1 M"'                                          ______________________________________                                    

The distinction between the state M" and M"' can be made, for example,by initially applying a fixed level to the first cell connection 1,precharging the bit line at the cell connection 2 to a precharged level,where the latter differs from the fixed level at the cell connection 1,and subsequently assessing the change in the bit line potentialfollowing activation of the memory cell. After this, the fixed level isapplied to the cell connection 2, the bit line at the cell connection 1is precharged and the change in potential of the bit line is assessedonce more.

The assessment can also be carried out by initially applying a firstfixed level to the cell connection 1 and assessing the level of the bitline at the cell connection 2 and, after this, applying a second fixedlevel to the cell connection 1 and once more assessing the level of thebit line at the cell connection 2.

The memory cell according to the invention is particularly suitable, forexample, for one-time programmable memories (OTP). The programming canbe carried out here by local injection of electrons into anoxide-nitride-oxide layer (ONO), which represents at least oneconstituent of the insulation layer ISO of the MOS field-effecttransistor, or else into a conventional oxide layer. When injecting"hot" charges at a high VDS, these charges are in this case injectedinto a small region in the vicinity of the drain region. The advantagesof so-called ONO layers over conventional oxide layers are that theyhave a high capture probability for electrons and that there isvirtually no lateral movement of these charges. The state according toFIG. 3 can be effected by homogeneous injection.

A further embodiment of the invention is constituted by the channelregion in the vicinity of one connection having a different doping thanthe rest of the channel of the MOS field-effect transistor. This can beeffected, for example, by means of an implantation mask, the opening ofwhich covers only part of the channel region. It is also possible for anadditional doping to be implanted at the drain before the source/drainimplantation and with the source region covered, for example, and to bediffused into the channel from the drain side of the transistor.

The mask required for this is self-aligning and therefore less critical.It is further conceivable to carry out the source/drain implantationsoptionally at shallow and at acute angles. Implantation at acute angles,for example of 0 to approximately 7 degrees, is known from standardtechnologies. There is experience with shallow angles, for example of 30to 60 degrees, in the development of LATID transistors(Large-Angle-Tilted-Implanted-Drain). The mask for the implantation at ashallow angle is relatively non-critical, since it has to overlap therelevant source/drain regions only in the transition region to the gateoxide and may arbitrarily overlap the channel region.

As an alternative to increasing the threshold voltage, it is alsopossible to reduce the threshold voltage, for example by introducingpositive charges.

Furthermore, corresponding memory elements can be realized, of course,not only using n-channel transistors, but also using p-channeltransistors.

In order to produce the asymmetry of the transistor, it is conceivablenot only to influence the threshold voltage, but also, for example, tochange the oxide thickness or have different transistor widths near tothe source and/or drain connection.

Furthermore, when the memory cell is being read out, it is possible todistinguish between three different transistor states in that thetransistor is operated either in the linear region, that is to say witha drain-source voltage VDS which is less than the gate voltage reducedby the threshold voltage VT (VDS<VG-VT), or in the saturation region. Inthis case, the polarity of the connections is not changed, but ratheronly the level of the voltage difference between the cell connection 1and the cell connection 2 is changed. The threshold voltages produced atthe different operating points are shown in the following table.

    ______________________________________                                        FIG.  VT where V21 > V31                                                                           VT where V21 ≅ V31                                                                 Cell inf.                                 ______________________________________                                        2A    low            low            0 M                                       2B    high           low            1 M'                                      2D, 3 high           high           2 M"'                                     ______________________________________                                    

In addition to producing symmetry or asymmetry within the MOS transistorT, the symmetry or asymmetry is brought about in a further embodiment byadditional components, such as diodes or resistors.

FIG. 4 illustrates an MOS field-effect transistor, the source/drainregion of which is connected via a diode D1 to the cell connection 1,the drain/source region of which is connected via a diode D2 to the cellconnection 2 and the gate connection of which is connected to the cellconnection 3. Depending on the programming, the diode D1 can be bridgedhere by an electrically conductive link K and the diode D2 by anelectrically conductive link K'. The manner in which four differentstates can be stored in a corresponding memory cell by this means can beinferred from the following table.

    ______________________________________                                        Diode at cell                                                                 connection  V(2) - V(1)                                                                             Cell state   Cell inform.                               ______________________________________                                        --          >0        on           0 0 M                                                  <0        on                                                      1           >0        off          0 1 M'                                                 <0        on                                                      2           >0        on           1 0 M"                                                 <0        off                                                     1 and 2     >0        off          1 1 M"'                                                <0        off                                                     ______________________________________                                    

FIG. 5 shows a sectional diagram of an advantageous embodiment of thememory cell of FIG. 4, a p⁺ -type region being inserted into thesource/drain region S/D, which is n⁺ -doped, for example, in this case,in order to form the diode D1 and a p⁺ -type region likewise beinginserted into the drain/source region D/S, which is n⁺ -doped, forexample, in this case, in order to form the diode D2. For the purpose ofprogramming, the diodes can be bridged, in a mask-programmable read-onlymemory (ROM), by means of contact holes, which are etched through the p⁺-type region as far as the n⁺ -doped source/drain region or drain/sourceregion and contains contact links K and K'. Programming can thereforetake place by means of an additional contact hole mask.

For electrical programming, the diodes must be able to be bridgedindividually. This can take place, for example, by application of a highvoltage, which produces a permanent conductive link by burning throughan oxide isolation layer, for example.

As an alternative, it is also possible individually to interruptoriginally existing conductive links by fuse blowing.

FIG. 6 differs from FIG. 4 only in that resistors R1 and R2 are providedinstead of the diodes D1 and D2. Asymmetry can be produced here byvirtue of the fact that a resistor in the source supply line leads to agreater current decrease than a resistor in the drain supply line.

The resistance of the cell connection regions can be altered by thedensity of the dopants and the depth of the doped region. The contacthole resistance can also be influenced by production, for example by thedesign of the barrier. Programming can likewise take place, as describedin the case of the embodiment of FIG. 4, by means of an additional maskor electrically.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. Multi-value read-only memory cell, havingsymmetrical construction for storing one of a first state and a secondstate and having asymmetrical construction for storing at least a thirdstate, comprising:a MOS field-effect transistor having a source/drainregion situated in a semiconductor body and having a drain/source regionsituated in the semiconductor body; in order to store the first state, afirst cell connection connected directly to the source/drain region ofthe MOS field-effect transistor and a second cell connection connecteddirectly to the drain/source region of the MOS field-effect transistor;in order to store the second state, the first cell connection connectedvia a first component to the source/drain region of the MOS field-effecttransistor, and the second cell connection connected via a secondcomponent to the drain/source region of the MOS field-effect transistor;in order to store the third state, the first cell connection connectedvia the first component to the source/drain region of the MOSfield-effect transistor, and the second cell connection connecteddirectly to the drain/source region of the MOS field-effect transistor;in order to store a fourth state, the first cell connection connecteddirectly to the source/drain region of the MOS field-effect transistor,and the second cell connection connected via the second component to thedrain/source region of the MOS field-effect transistor; a third cellconnection connected to a gate electrode of the MOS field-effecttransistor, the gate electrode being electrically insulated from thesemiconductor body by an insulation layer (ISO); and the first componentbeing a first diode and the second component being a second diode. 2.The multi-value read-only memory cell according to claim 1,wherein, inorder to form the first diode, the first cell connection is connectedvia a first supplementary region to the source/drain region of the MOSfield-effect transistor and, in order to form the second diode, thesecond cell connection is connected via a second supplementary region tothe drain/source region of the MOS field-effect transistor; wherein, inorder to store the first state, first and the second supplementaryregions are bridged by metallic contact links of the first and secondconnections, which contact links have a deep structure and extend atleast as far as the source/drain region and drain/source region;wherein, in order to store the second state, both the first and thesecond supplementary regions are contacted only by metallic contactlinks of the first and second connections, which contact links have aplanar configuration and extend only at least as far as the first andsecond supplementary regions; wherein, in order to store the thirdstate, only the first supplementary region is bridged by a metalliccontact link of the first connection, which contact link has a deepstructure and extends at least as far as the source/drain region; andwherein, in order to store the fourth state, only the secondsupplementary region is bridged by a metallic contact link of the firstconnection, which contact link has a deep structure and extends at leastas far as the drain/source region.
 3. A multi-value read-only memorycell, having symmetrical construction for storing a first state and asecond state and having asymmetrical construction for storing at least athird state, comprising:a MOS field-effect transistor having asource/drain region situated in a semiconductor body and having adrain/source region situated in the semiconductor body; in order tostore the first state a first cell connection connected directly to thesource/drain region of the MOS field-effect transistor, and a secondcell connection connected directly to the drain/source region of the MOSfield-effect transistor; in order to store the second state, the firstcell connection connected via a first component to the source/drainregion of the MOS field-effect transistor and the second cell connectionconnected via a second component to the drain/source region of the MOSfield-effect transistor; in order to store the third state, the firstcell connection connected via the first component to the source/drainregion of the MOS field-effect transistor, and the second cellconnection connected directly to the drain/source region of the MOSfield-effect transistor; in order to store a fourth state, the firstcell connection connected directly to the source/drain region of the MOSfield-effect transistor, and the second cell connection connected viathe second component to the drain/source region of the MOS field-effecttransistor; a third cell connection connected to a gate electrode of theMOS field-effect transistor, the gate electrode being electricallyinsulated from the semiconductor body by an insulation layer; and thefirst component being a first resistor and the second component being asecond resistor.